The present invention relates to a BICMOS process used in fabricating a self-aligned non-selective thin-epi-base silicon germanium (SiGe), heterojunction bipolar transistor (HBT), and particularly to a SiGe HBT BiCMOS process using silicon dioxide etchback.
The first fabrication process used for making commercial chips was the bipolar process, called so because it was used for making bipolar transistors, however, it was limited in size and power. Next, the chips were made using MOS technology with either pMOS or nMOS. At about the same time the CMOS (complementary MOS) process was developed in which pMOS and nMOS devices coexisted on the same chip. More recently, with a few extra fabrication steps, processes were developed to make both CMOS devices and optimized bipolar transistors. These are called BiCMOS (bipolar CMOS) processes. Such processes add flexibility to circuit design at a increased fabrication cost. The last few years have seen rapid progress in techniques for the deposition of both epitaxial layers of silicon as well as pseudomorphic SiGe epitaxial layers for the bipolar transistor. The SiGe material set can provide a path to heterojunction device physics and applications within the well established (CMOS dominated) silicon-based semiconductor industry.
In recent years, a photoresist etchback process has been proposed to fabricate SiGe HBT""s. There is a general need for alternate fabrication processes to manufacture SiGe HBT""s. More specifically, a need exists for processes, other than photoresist etchback processes, for removing the unwanted SiGe film in the field areas around the heterojunction bipolar transistors.
The invention describes a process of making self-aligned Heterojunction Bipolar Transistors (HBT). The HBT is made with Silicon Germanium (SiGe), becoming known as a SiGe HBT. The present invention describes a process of making the SiGe HBT which does not use photoresist etchback. Instead, in one embodiment of the present invention, a TEOS silicon dioxide etchback is used. In another embodiment, a Spin-On-Glass (SOG) silicon dioxide etchback is used.
A typical BiCMOS process includes a silicon bipolar transistor, a NMOS transistor and a PMOS transistor. In this case the bipolar transistor shown is a SiGe Heterojunction Bipolar Transistor (HBT). The BiCMOS base has the three devices fabricated on a P-Substrate. Each of the devices in the BiCMOS base are separated by Deep Trench Isolation, with each deep trench topped with a field oxide layer and a gate oxide layer covering the rest of the BiCMOS base.
On top of the BiCMOS base, a plurality of polysilicon features are deposited. Multiple layers are next deposited over the structure. The multiple layers include silicon dioxide, a thin protection layer of polysilicon, another protection layer of silicon dioxide and a seed layer of polysilicon. A well is formed in the multiple layers by masking and etching the gate oxide, polysilicon layer, the silicon dioxide layer, the polysilicon protection layer, the silicon dioxide protection layer and the polysilicon seed layer. After etching, a non-selective thin epi base of silicon germanium (SiGe) is deposited.
In a first embodiment, a thick layer of TEOS plasma silicon dioxide is non-selectively deposited on the SiGe, filling the well. Optionally, to. fill in the cracks and smooth out the upper surface of the TEOS plasma silicon dioxide, a layer of Spin-on-Glass (SOG) silicon dioxide may be deposited on the TEOS plasma silicon dioxide layer and cured. In an alternate embodiment, the TEOS plasma silicon dioxide layer may omitted and SOG silicon dioxide is used to fill the well.
The TEOS plasma silicon dioxide and/or the SOG silicon dioxide layer is etched until the remaining portion fills approximately one half the well. Next, an anisotropic polysilicon etch is done removing the SiGe layer outside the well area (i.e., from the xe2x80x9cfield areaxe2x80x9d) and also the top portion of the SiGe layer on the upper walls of the well. Also etched during this process is the polysilicon seed layer. A thin silicon nitride layer is non-selectively deposited on the TEOS plasma silicon dioxide layer and the silicon dioxide protection layer. This silicon nitride is then etched back to cover only the upper walls of the well. A Buffered Oxide Etch (BOE) is done to remove the TEOS plasma silicon dioxide layer and the silicon dioxide protection layer. The well is now lined with the SiGe base layer along the bottom and lower porion of the walls of the well with silicon nitride layers at the upper wall, contiguous with the SiGe layer.
Layers of silicone dioxide, silicon nitride, a spacer layer of polysilicon are non-selectively deposited on the surface. The polysilicon spacer layer and silicon nitride layer are then plasma etched back (anisotropic) until the only portion remaining of the layers fill the lower corners of the well. A silicon dioxide dip etch is next, which completely removes the polysilicon spacer layer and silicon dioxide protection layer. An emitter polysilicon deposition with a N+ implant is deposited next and is masked and etched to create the SiGe heterojunction bipolar transistor.
Other objects and advantages of the present invention will become apparent upon reading the following description taken together with the accompanying drawings.